CS302- Digital Logic Design Quiz

Question # 1 of 10 ( Start time: 03:03:55 PM )  Total Marks: 1  

Divide-by-32 counter can be acheived by using  
Select correct option:  

Flip-Flop and DIV 10 
Flip-Flop and DIV 16 
Flip-Flop and DIV 32 
DIV 16 and DIV 32

Question # 2 of 10 ( Start time: 03:05:20 PM )  Total Marks: 1  
The counter states or the range of numbers of a counter is determined by the formula. (“n” represents the total number of flip-flops)  
Select correct option:  

(n raise to power 2) 
(n raise to power 2 and then minus 1) 
(2 raise to power n)
(2 raise to power n and then minus 1)

Question # 3 of 10 ( Start time: 03:06:36 PM )  Total Marks: 1  
A 4- bit UP/DOWN counter is in DOWN mode and in the 1010 state. on the next clock pulse, to what state does the counter go?  
Select correct option:  

1001 
1011 
0011 
1100

Question # 4 of 10 ( Start time: 03:07:37 PM )  Total Marks: 1  
A 4-bit binary UP/DOWN counter is in the binary state zero. the next state in the DOWN mode is___________  
Select correct option:  

0001 
1111 
1000 
1110

Question # 5 of 10 ( Start time: 03:09:04 PM )  Total Marks: 1  
Divide-by-160 counter is acheived by using  
Select correct option:  

Flip-Flop and DIV 10 
Flip-Flop and DIV 16 
DIV 16 and DIV 32 
DIV 16 and DIV 10

Question # 6 of 10 ( Start time: 03:10:01 PM )  Total Marks: 1  
A counter is implemented using three (3) flip-flops, possibly it will have ______ maximum output status.  
Select correct option:  

3 
7 
8 
15

Question # 7 of 10 ( Start time: 03:10:49 PM )  Total Marks: 1  
RCO stands for ________  
Select correct option:  

Reconfiguration Counter Output 
Ripple Counter Output 
Reconfiguration Clock Output 
Ripple Clock Output

Question # 8 of 10 ( Start time: 03:11:38 PM )  Total Marks: 1  
__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.  
Select correct option:  

Race condition 
Clock Skew 
Ripple Effect 
None of given options

Question # 9 of 10 ( Start time: 03:12:20 PM )  Total Marks: 1  
For a down counter that counts from (111 to 000), if current state is "101" the next state will be _______  
Select correct option:  

111 
110 
010 
none of given options

Question # 10 of 10 ( Start time: 03:13:03 PM )  Total Marks: 1  
A Divide-by-20 counter can be acheived by using  
Select correct option:  

Flip-Flop and DIV 10 
Flip-Flop and DIV 16 
Flip-Flop and DIV 32 
Div 10 and DIV 16

Q :  Ripple Clock Output

The 74HC163 is a 4-bit Synchronous Counter.it has..............data output pins
Select correct option:

2
4 
6
8

Q :  __________ Counters as the name indicates are not triggered simultaneously
Select correct option:

Asynchronous 
Synchronous
Positive-Edge triggered

Negative-Edge triggered

Q :  A counter is implemented using three (3) flip-flops, possibly it will have ______ maximum output status.
Select correct option:

3 
7 
8 
15

Q :  Design of state diagram is one of many steps used to design
Select correct option:

a clock 
a truncated counter 
an UP/DOWN counter 
any counter

Q :  A synchronous decade counter will have _____ flip-flops
Select correct option:

3 
4 
7 
10

Q :  Karnaugh map is used in designing
Select correct option:

a clock 
a counter 
an UP/DOWN counter 
All of the above

Q :  __________ is said to occur when multiple internal variables change due to change in one input variable
Select correct option:

Hold and Wait 
Clock Skew 
Race condition 
Hold delay

Q :  Three cascaded modulus-10 counters have an overall modulus of
Select correct option:

30 
100 
1000 
10000

Q :  An Astablemultivibrator is known as a(n) _____ 
Select correct option:

Oscillator 
Booster 
One-shot 
Dual-shot

Q: __________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.  
Select correct option:  

Race condition 
Clock Skew 
Ripple Effect 
None of given options

Q:The glitches due to "Race Condition" can be avoided by using a _________  
Select correct option:  

Gated flip-flops
Pulse triggered flip-flops
Positive-Edge triggered flip-flops
Negative-Edge triggered flip-flops

Q: In case of cascading Integrated Circuit counters, the enable inputs and RCOof the Integrated Circuit counters allow cascading of multiple counters together  
Select correct option:  

True 
False

Quiz:  A flip-flop is presently in SET stae and must remain SET on the next cliock pulse. What must j and K be?
Select correct option:

J = 1, K = 0 
J = 1, K = X(Don't care) 
J = X(Don't care), K = 0 
J = 0, K = X(Don't care)

Q: The Synchronous counters are also known as Ripple Counters:  
Select correct option:  

True 
False

Q:A decade counter can be implemented by truncating the counting sequence of a MOD-20 counter.  
Select correct option:  

True 
False

Quiz:  The terminal count of a 4-bit binary counter in the DOWN mode is__________ 
Select correct option:

0000 
0011 
1100 
1111

Quiz:  An Asynchronous Down-counter is implemented (Using J-K flip-flop) by connecting______ 
Select correct option:

Q output of all flip-flops to clock input of next flip-flops 
Q’ output of all flip-flops to clock input of next flip-flops 
Q output of all flip-flops to J input of next flip-flops 
Q’ output of all flip-flops to K input of next flip-flops

the terminal count of a modulus-13 binary counter is  
Select correct option:  

0000 
1111 
1101 
1100

Quiz:  A decade counter can be implemented by truncating the counting sequence of a MOD-20 counter.
Select correct option:

True 
False

Quiz:  A 4- bit UP/DOWN counter is in DOWN mode and in the 1010 state. on the next clock pulse, to what state does the counter go?
Select correct option:

1001 
1011 
0011 
1100

Quiz:  Design of state diagram is one of many steps used to design
Select correct option:

a clock 
a truncated counter 
an UP/DOWN counter 
any counter

 Quiz:  An Astablemultivibrator is known as a(n) _____ 
Select correct option:

Oscillator 
Booster 
One-shot 
Dual-shot

 Quiz:  The glitches due to "Race Condition" can be avoided by using a _________ 
Select correct option:

Gated flip-flops
Pulse triggered flip-flops
Positive-Edge triggered flip-flops
Negative-Edge triggered flip-flops

 Quiz:  A decade counter is ________ 
Select correct option:

Mod-3 counter 
Mod-5 counter 
Mod-8 counter 
Mod-10 counter

Question # 1 of 10 ( Start time: 03:40:29 PM )         Total Marks: 1
The terminal count of a 4-bit binary counter in the DOWN mode is__________
Select correct option:
       0000
       0011
       1100
       1111

Question # 2 of 10 ( Start time: 03:40:50 PM )         Total Marks: 1
The Synchronous counters are also known as Ripple Counters:
Select correct option:
       True
       False

Question # 3 of 10 ( Start time: 03:41:08 PM )         Total Marks: 1
__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
Select correct option:
       Race condition
       Clock Skew
       Ripple Effect
       None of given options

Question # 4 of 10 ( Start time: 03:41:27 PM )         Total Marks: 1
Divide-by-160 counter is acheived by using
Select correct option:
       Flip-Flop and DIV 10
       Flip-Flop and DIV 16
       DIV 16 and DIV 32
       DIV 16 and DIV 10

Question # 5 of 10 ( Start time: 03:41:44 PM )         Total Marks: 1
Design of state diagram is one of many steps used to design
Select correct option:
       a clock
       a truncated counter
       an UP/DOWN counter
       any counter

Question # 6 of 10 ( Start time: 03:42:01 PM )         Total Marks: 1
In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is__________
Select correct option:
       0000
       1111
       0001
       10000